FPGA TUTORIALS

What is the Testbench? FPGA Simulation, TCL – Tool Command Language

Tháng tám 4, 2024

Before reading this article, you should read the article about HDLs: (LINK HERE )

The Github folder for this article: (LINK HERE)

1./ What is the Testbench:

+ One of the main uses of an HDL is that of simulating a new design to ensure that the design is correct. To simulate a design, we need to set the design’s inputs to certain values, and then check that the design’s output values are what we expect them to be. A system that sets input values and checks output values is known as a testbench.

+ Creating test benches for your FPGA design is a critical step for any FPGA design project. The VHDL, Verilog test benches are used for the simulation and verification of FPGA designs.

+ The Testbench does not contain any external ports, just internal signals that connect the two instantiated components. Testbench automatically generates inputs and checks the output with the provided inputs.

+ FPGA Software provides HDL Simulators, you can look up information here: List of HDL Simulators.

2./ TestBench Structure

The testbench has two main components:

  • The first being the Design Under Test (DUT) or the Unit Under Test (UUT), the Design Under Verification (DUV).
  • The second the stimulus driver.

A testbench is used to verify the functionality of a design.
A testbench is at the highest level in the hierarchy of the design (The top-level design). The testbench instantiates the design under test (DUT). The testbench provides the necessary input stimulus to the DUT and examines the output from the DUT.

=> The stimulus driver drives inputs into the DUT.

There are two ways to create input stimulus:

  • Using an interactive waveform editor (easy).
  • Using a testbench (a bit harder).

=> The DUT responds to the input signals and produces output results.

=> Finally, a compare function within the testbench compares the results from the DUT against those known good results and reports any discrepancies.

3./ Programming language for TestBench

Let’s learn about Programming languages for TestBench through examples.
We will learn how to write TestBench for programs with AND Gate, so you can grasp the problem as quickly as possible. If you start learning about TestBench for complex designs, it will be harder for you to approach and understand the problem.

3.1./ VHDL testbench

=> Attention: VHDL code of AND gate, you read in this link about HDLs.

We will write a VHDL testbench for this AND gate.

3.1.1./ Write VHDL testbench and run on Quartus, ModelSim

  1. -- Vhdl Test Bench template for design  :  ANDGATE
  2. -- 
  3. -- Simulation tool : ModelSim-Altera (VHDL)
  4. -- 
  6. LIBRARY ieee;                                               
  7. USE ieee.std_logic_1164.all;                                
  9. ENTITY ANDGATE_vhd_tst IS
  10. END ANDGATE_vhd_tst;
  12. ARCHITECTURE ANDGATE_arch OF ANDGATE_vhd_tst IS
  13. -- constants                                                 
  14. -- signals                                                   
  15. SIGNAL I1 : STD_LOGIC;
  16. SIGNAL I2 : STD_LOGIC;
  17. SIGNAL O : STD_LOGIC;
  18. COMPONENT ANDGATE
  19. 	PORT (
  20. 	I1 : IN STD_LOGIC;
  21. 	I2 : IN STD_LOGIC;
  22. 	O : OUT STD_LOGIC
  23. 	);
  24. END COMPONENT;
  26. BEGIN
  27. 	dut : ANDGATE
  28. 	PORT MAP (
  29. -- list connections between master ports and signals
  30. 	I1 => I1,
  31. 	I2 => I2,
  32. 	O => O
  33. 	);
  34. init : PROCESS                                               
  35. -- variable declarations                                     
  36. BEGIN                                                        
  37.         -- code that executes only once 
  38.         I1 <= '0';
  39.         I2 <= '0';
  40.         wait for 1 ps;
  41.         I1 <= '0';
  42.         I2 <= '1';
  43.         wait for 1 ps;
  44.         I1 <= '1';
  45.         I2 <= '0';
  46.         wait for 1 ps;
  47.         I1 <= '1';
  48.         I2 <= '1';
  49.         wait for 1 ps;                     
  50. WAIT;                                                       
  51. END PROCESS init;                                           
  52. always : PROCESS                                              
  53. -- optional sensitivity list                                  
  54. -- (        )                                                 
  55. -- variable declarations                                      
  56. BEGIN                                                         
  57.         -- code executes for every event on sensitivity list  
  58. WAIT;                                                        
  59. END PROCESS always;                                          
  60. END ANDGATE_arch;

3.1.2./ Write VHDL testbench and run on Vivado

  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use std.env.finish;
  5. -- creat VHDL testbench entity has no input or output
  6. entity and_vhdl_tb is
  7.     end entity and_vhdl_tb;
  9. -- describe the architecture of VHDL testbench entity
  10. architecture behave of and_vhdl_tb is 
  11.     signal r_I1: std_logic;
  12.     signal r_I2: std_logic;
  13.     signal w_O: std_logic;
  14. begin
  15.     -- instantiate the uut, using and_vhdl entity in and_vhdl_tb architecture
  16.     -- the Working Library: contains the compiled version of your design. The contents of a working library change every time you compile your design.
  17.     -- the default working library is named "work"
  18.     uut : entity work.and_vhdl
  19.         port map(
  20.             I1 => r_I1,
  21.             I2 => r_I2,
  22.             O => w_O      
  23.         );
  24.     -- start at the begining of the simulation
  25.     process is
  26.         begin
  27.             r_I1 <= '0';
  28.             r_I2 <= '0';
  29.             wait for 5ps;
  30.             r_I1 <= '0';
  31.             r_I2 <= '1';
  32.             wait for 5ps;
  33.             r_I1 <= '1';
  34.             r_I2 <= '0';
  35.             wait for 5ps;
  36.             r_I1 <= '1';
  37.             r_I2 <= '1';
  38.             wait for 5ps;
  39.             --finish;
  40.             wait;
  41.     end process;
  42. end behave;

3.2./ Verilog testbench

=> Attention: Verilog code of AND gate, you read in this link about HDLs.

We will write a Verilog testbench for this AND gate.

3.2.1./ Write Verilog testbench and run on Quartus, ModelSim

  1. // Verilog Test Bench template for design : and_verrilog
  2. // 
  3. // Simulation tool : ModelSim-Altera (Verilog)
  4. // 
  6. `timescale 1 ps/ 1 ps
  7. module and_verrilog_vlg_tst();
  8. // constants                                           
  9. // general purpose registers
  10. reg eachvec;
  11. // test vector input registers
  12. reg a;
  13. reg b;
  14. // wires                                               
  15. wire c;
  17. // assign statements (if any)                          
  18. and_verrilog i1 (
  19. // port map - connection between master ports and signals/registers   
  20. 	.a(a),
  21. 	.b(b),
  22. 	.c(c)
  23. );
  24. initial                                                
  25. begin                                                  
  26. // code that executes only once                        
  27. // insert code here --> begin                          
  28.   a = 0;             
  29.   b = 0;                                                     
  30. // --> end                                             
  31. $display("Running testbench");                       
  32. end                                                    
  33. always                                                 
  34. // optional sensitivity list                           
  35. // @(event1 or event2 or .... eventn)                  
  36. begin                                                  
  37. // code executes for every event on sensitivity list   
  38. // insert code here --> begin                          
  39.   $dumpfile("and_verilog_test.vcd"); $dumpvars;
  40.   $monitor("Time= %3d : a= %d,b= %d, c=%d \n",$time,a,b,c);
  41.   a <= 1'b0;
  42.   b <= 1'b0;
  43.   #5;
  44.   $monitor("Time= %3d : a= %d,b= %d, c=%d \n",$time,a,b,c);
  45.   a <= 1'b0;
  46.   b <= 1'b1;
  47.   #5;   
  48.   $monitor("Time= %3d : a= %d,b= %d, c=%d \n",$time,a,b,c);
  49.   a <= 1'b1;
  50.   b <= 1'b0;
  51.   #5;  
  52.   $monitor("Time= %3d : a= %d,b= %d, c=%d \n",$time,a,b,c);
  53.   a <= 1'b1;
  54.   b <= 1'b1;
  55.   #5;
  56.   $display("Finish testbench");  
  57.                                                        
  58. @eachvec;                                              
  59. // --> end                                             
  60. end                                                    
  61. endmodule

3.2.2./ Write Verilog testbench and run on Vivado

  1. // Verilog Test Bench template for design : and_verrilog
  2. // 
  3. // Simulation tool : Xilinx Vivado (Verilog)
  4. // 
  5. `timescale 1 ps/ 1 ps
  6. module and_verrilog_vlg_tst();
  7. // test vector input registers
  8. reg a;
  9. reg b;
  10. // wires                                               
  11. wire c;
  12. // assign statements (if any)                          
  13. and_verrilog i1 (
  14. // port map - connection between master ports and signals/registers   
  15. 	.a(a),
  16. 	.b(b),
  17. 	.c(c)
  18. );
  19. initial                                                
  20. begin                                                  
  21. // code that executes only once                        
  22. // insert code here --> begin                          
  23.   a = 0;             
  24.   b = 0;                                                     
  25. // --> end                                             
  26. $display("Running testbench");                       
  27. end                                                    
  28. always                                                 
  29. // optional sensitivity list                           
  30. // @(event1 or event2 or .... eventn)                  
  31. begin                                                  
  32. // code executes for every event on sensitivity list   
  33. // insert code here --> begin                          
  34.   $dumpfile("and_verilog_test.vcd"); $dumpvars;
  35.   $monitor("Time= %3d : a= %d,b= %d, c=%d \n",$time,a,b,c);
  36.   a <= 1'b0;
  37.   b <= 1'b0;
  38.   #5;
  39.   $monitor("Time= %3d : a= %d,b= %d, c=%d \n",$time,a,b,c);
  40.   a <= 1'b0;
  41.   b <= 1'b1;
  42.   #5;   
  43.   $monitor("Time= %3d : a= %d,b= %d, c=%d \n",$time,a,b,c);
  44.   a <= 1'b1;
  45.   b <= 1'b0;
  46.   #5;  
  47.   $monitor("Time= %3d : a= %d,b= %d, c=%d \n",$time,a,b,c);
  48.   a <= 1'b1;
  49.   b <= 1'b1;
  50.   #5;
  51.   $display("Finish testbench");  
  52.                                                                                                     
  53. // --> end                                             
  54. end                                                    
  55. endmodule

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