Verilog
VHDL
ALTERA FPGA
XILINX FPGA
What is the Testbench? FPGA Simulation, TCL – Tool Command Language
Before reading this article, you should read the article about HDLs: (LINK HERE ) The Github folder for this article: (LINK HERE) 1./ What is the Testbench: + One of the main uses of an HDL is that of simulating…
HDL – Hardware Description Language, VHDL, Verilog
The Github folder for this article: (LINK HERE) 1./ Introduce about HDL Hardware Description Language (HDL) is a specialized computer language used to describe the structure, behavior and timing of electronic circuits, digital circuit, most commonly to design ASICs and…
The AND gate
The AND gate with two-input (A,B), one output (Y). The AND gate reminds us of an electrical circuit with 2 switches A, B and 1 light bulb Y. Y=TRUE if and only if both A and B are TRUE. Otherwise,…
What is Look-Up Tables (LUTs) in FPGA (Look-Up Tables, LUT là gì?)
In this article we explore two questions: 1./ What is Look-Up Table (LUT)? Look-Up Table là gì? + What is Look-Up Tables (LUT): LUT or Look-Up Table, is a table that determines output values for combinations of input values, it…
List of FPGA Tutorials
Table of Contents for FPGA Tutorials, you can access the links of the articles to read detailed content. [FPGA Toturial] github repository was created to support this list: https://github.com/ThuyPham/FPGA-Toturial[FPGA Tutorial thuypx.com] playlist YouTube: (LINK) 1./ What is an FPGA? 2./…
ABOUT ME
Hello,I’m Thuy, a programmer and writer.I love programming, learning about technologies, applying them in practice, and writing. I came to FPGA accidentally one day when I felt curious, interested and wanted to do more about FPGA. I created thuypx.com in…
FPGA, Embedded System, Thùy Mê Code
